A phase locked loop is, in essence, an oscillator that tries to match the frequency of – or more importantly, a division or multiple of the frequency of – another signal. This is most commonly used to create a frequency that is much higher than the incoming reference signal – such as a timing module that can create an output clock that is 2, 4, 8, or more times the tempo of an incoming clock, or a very high frequency oscillator that is locked to a multiple of an incoming pitch – perhaps to drive a special circuit such as a switched-capacitor filter.
The problem and opportunity is that it’s very hard for a PLL to exactly, tightly follow change in the incoming reference pitch. A circuit (the phase comparator) needs to detect a difference between the input and the PLL’s oscillator and send a change in voltage to that oscillator; this voltage is usually smoothed by a slew or filter circuit to get rid of noise and other small wiggles in the difference. Therefore, a PLL tends to lag behind changes in the input signal.
A couple of examples of modules that expose the inner workings of a PLL to the user are the Doepfer A-196 and WMD Synchrodyne – see the links below. A clocking module like the 4ms Quad Clock Distributor is a good example of an internal PLL applied to timing signals.
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